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DTSTAMP:20210402T160557Z
LOCATION:Track 7
DTSTART;TZID=America/New_York:20201113T133000
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UID:submissions.supercomputing.org_SC20_sess226_ws_ross103@linklings.com
SUMMARY:Ch’i: Scaling Microkernel Capabilities in Cache-Incoherent Systems
DESCRIPTION:Workshop\n\nCh’i: Scaling Microkernel Capabilities in Cache-In
 coherent Systems\n\nRen, Parmer, Milojicic\n\nHardware cache coherence lim
 its the scalability of shared-memory multicore and multi-processors. Recen
 tly, there has been an increasing shift toward cache-incoherent architectu
 res in many computing environments. Supercomputers can benefit from shared
  memory, yet must avoid the price of coherency across the system. To suppo
 rt co-locating multiple applications on cores, processors and the overall 
 system, an operating system (OS) must manage the distributed memory resour
 ces. In this context, incoherence poses a significant challenge for an OS 
 that must manage memory access permissions across the system without compr
 omising the performance of software.\n\nIn this paper, we introduce the Ch
 ’i microkernel that leverages incoherent shared memory using quiescence-ba
 sed techniques to bound the extent of non-coherency. Ch’i maintains type a
 nd context consistency of its core data structures: capabilities. This ena
 bles a uniform, capability-based security model to manage system-wide memo
 ry. Using this approach, we demonstrate data-structure consistency in soft
 ware in support of high-throughput, low-latency applications.\n\nTag: Syst
 em Software and Runtime Systems\n\nRegistration Category: Workshop Reg Pas
 s
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