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LOCATION:Track 1
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UID:submissions.supercomputing.org_SC20_sess193@linklings.com
SUMMARY:HiPar20: Workshop on Hierarchical Parallelism for Exascale Computi
 ng
DESCRIPTION:Workshop\n\nHiPar20 – Break\n\n\n\n---------------------\nHiPa
 r20 – Invited Talk: Glow: a Machine Learning Compiler and Execution Engine
 \n\nFix\n\n---------------------\nHiPar20 – Introduction: Workshop on Hier
 archical Parallelism for Exascale Computing\n\nRizzi, Hollman, Li, Howes\n
 \nHigh-Performance Computing (HPC) platforms are evolving toward having fe
 wer but more powerful nodes, driven by the increasing number of physical c
 ores in multiple sockets and accelerators. The boundary between nodes and 
 networks is starting to blur, with some nodes now containing tens of compu
 te ele...\n\n---------------------\nA Case Study and Characterization of a
  Many-Socket, Multi-Tier NUMA HPC Platform\n\nImes, Hofmeyr, Kang, Walters
 \n\nAs the number of processor cores and sockets on HPC compute nodes incr
 ease and systems expose more hierarchical non-uniform memory access (NUMA)
  architectures, efficiently scaling applications within even a single shar
 ed memory system is becoming more challenging. It is now common for HPC co
 mpute no...\n\n---------------------\nHiPar20 – Closing Remarks\n\nRizzi, 
 Hollman, Li, Howes\n\n---------------------\nHiPar20 – Keynote 1: Exploiti
 ng Hierarchical Algorithms on Ever More Hierarchical Architectures\n\nClar
 k\n\n---------------------\nHiPar20 – Break\n\n\n\n---------------------\n
 HiPar20: Keynote 2: Single-Level Programming on Hierarchical Hardware via 
 Adaptive Runtime? Maybe\n\nKale\n\n---------------------\nHiPar20 – Break\
 n\n\n\n---------------------\nUsing Hierarchical Parallelism to Accelerate
  the Solution of Many Small Partial Differential Equations\n\nMerson, Shep
 hard\n\nThis paper presents efforts to improve the hierarchical parallelis
 m of a two scale simulation code. Two methods to improve the GPU parallel 
  performance were developed  and compared.  The first used the  Nvidia Mul
 ti-Process Service and the second moved the entire sub-problem loop into a
  single kern...\n\n---------------------\nFlexible Runtime Reconfigurable 
 Computing Overlay Architecture and Optimization for Dataflow Applications\
 n\nShah, Carrion Schafer\n\nMany computationally intensive applications ar
 e accelerated on FPGAs following the stream computing, also called dataflo
 w computing, paradigm.  This entails that data is streamed through differe
 nt components of a given application in wide deep pipelines to maximize th
 roughput. One of the main drawba...\n\n---------------------\nHiPar20 – In
 vited Talk: A Portable Asynchronous Tasking Approach to Hierarchical Paral
 lelism - Successes, Challenges, and Future Prospects\n\nBerzins\n\n-------
 --------------\nHiPar20 – Panel Session\n\nTrott, Demeshko, Alam, Chandras
 ekaran, Hofstee...\n\n---------------------\nIntroducing Multi-Level Paral
 lelism, at Coarse, Fine, and Instruction Level to Enhance the Performance 
 of Iterative Solvers for Large Sparse Linear Systems on Multi- and Many-Co
 re Architecture\n\nGratien\n\nMulti-core and many-core systems are now a c
 ommon feature of new hardware architectures. The introduction of a very la
 rge number of cores at the processor level requires multi-level parallelis
 m to fully take advantage of the offered computing power. The induced  pro
 gramming effort can be fixed with ...\n\n\nTag: Extreme Scale Computing, H
 eterogeneous Systems, Parallel Programming Languages, Libraries, and Model
 s, Portability, Resource Management and Scheduling, Scalable Computing\n\n
 Registration Category: Workshop Reg Pass
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