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LOCATION:Track 1
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UID:submissions.supercomputing.org_SC20_sess193_ws_hipar103@linklings.com
SUMMARY:A Case Study and Characterization of a Many-Socket, Multi-Tier NUM
 A HPC Platform
DESCRIPTION:Workshop\n\nA Case Study and Characterization of a Many-Socket
 , Multi-Tier NUMA HPC Platform\n\nImes, Hofmeyr, Kang, Walters\n\nAs the n
 umber of processor cores and sockets on HPC compute nodes increase and sys
 tems expose more hierarchical non-uniform memory access (NUMA) architectur
 es, efficiently scaling applications within even a single shared memory sy
 stem is becoming more challenging. It is now common for HPC compute nodes 
 to have two or more sockets and dozens of cores, but future generation sys
 tems may contain an order of magnitude more of each. We conduct experiment
 s on a state-of-the-art Intel Xeon Platinum system with 12 processor socke
 ts, totaling 288 cores (576 hardware threads), arranged in a multi-tier NU
 MA hierarchy. Platforms of this scale and memory hierarchy are uncommon to
 day, providing us a unique opportunity to empirically evaluate—rather than
  model or simulate—an architecture potentially representative of future HP
 C compute nodes. We quantify the platform’s multi-tier NUMA patterns, then
  evaluate its suitability for HPC workloads using a modern HPC metagenome 
 assembler application as a case study, and other HPC benchmarks with a var
 iety of parallelization techniques to characterize the system’s performanc
 e, scalability, I/O patterns, and performance/power behavior. Our results 
 demonstrate near- perfect scaling for embarrassingly parallel and weak sca
 ling workloads, but challenges for random memory access workloads. For the
  latter, we find poor scaling performance with the default scheduling appr
 oaches—e.g., which do not pin threads— suggesting that userspace or kernel
  schedulers may require changes to better manage the multi-tier NUMA hiera
 rchies of very large shared memory platforms.\n\nTag: Extreme Scale Comput
 ing, Heterogeneous Systems, Parallel Programming Languages, Libraries, and
  Models, Portability, Resource Management and Scheduling, Scalable Computi
 ng\n\nRegistration Category: Workshop Reg Pass
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